1. Field of the Invention
The invention relates to a method of and an apparatus for generating a pattern for testing a logic circuit, and more particularly to such a method and an apparatus which are capable of shortening a length of a test pattern generated by an automatic test pattern generation (ATPG) system used for a combinational circuit and an automatic test pattern generation system used for a sequential circuit.
2. Description of the Related Art
As a scale of an integrated circuit such as LSI has become larger recently, a cost for testing an integrated circuit becomes higher. One of factors on which a cost for testing an integrated circuit is dependent is the number of patters for testing an integrated circuit. Less the number of test patterns is, shorter a period of time necessary for testing an integrated circuit is, ensuring that it is possible to shorten a period of time for using an expensive LSI tester, and hence, testing costs can be significantly reduced. Accordingly, there is a need of a method of reducing the number of test patterns.
In general, a test pattern generated by an automatic test pattern generation (ATPG) system used for a sequential circuit is different from a test pattern generated by an automatic test pattern generation system used for a combinational circuit, as follows.
The first difference is that a fault can be always detected by means of a signal test pattern in a combinational circuit, whereas a plurality of test patterns has to be used for testing a fault in many cases in a sequential circuit. Accordingly, the number of test patterns generated by an ATPG system used for a sequential circuit is likely to increase.
The second difference is as follows. In test patterns generated by an ATPG system used for a combination system, even if arrangement of respective test patterns were varied, a fault detecting rate obtained in an original arrangement of test patterns is not reduced. In contrast, in test patterns generated by an ATPG system used for a sequential system, if arrangement of respective test patterns were varied, there is often obtained a fault detecting rate which is lower than a fault detecting rate obtained in all original arrangement of test patterns. The reason is as follows. Since a sequential circuit includes a memory such as flip-flop (F/F) circuit, a value transmitted through an output terminal of the sequential circuit at a certain time is dependent on both a test pattern having been input into an input terminal of the sequential circuit and a logical value of a flip-flop circuit or internal condition of the sequential circuit at the certain time. Accordingly, if arrangement of respective test patterns were varied, the internal condition of the sequential circuit is also varied, resulting in that a fault which can be detected before the arrangement is varied can be no longer detected.
There is an increasing need for shortening a length of a test pattern generated by an ATPG system used for a sequential circuit, that is, a need for strengthening a function of test pattern compaction.
For instance, Japanese Unexamined Patent Publication No. 2000-329831 published on Nov. 30, 2000 has suggested an apparatus for compacting test patterns used for a combinational circuit in an ATPG system (hereinafter, the Publication is referred to as first prior art).
Though the first prior art is explained later, it should be noted that the applicant does not admit that the first prior art constitutes statutory prior art to the present invention. The first prior art is referred to herein merely for the purpose of better understanding of the present invention.
Japanese Unexamined Patent Publication No. 5-341011 has suggested a method of generating a test pattern (hereinafter, the Publication is referred to as second prior art).
The article identified below provides explanation about test pattern compaction in a logic circuit: B. Ayari and B. Kaminska, xe2x80x9cA New Dynamic Test Vector Compaction for Automatic Test Pattern Generationxe2x80x9d, IEEE Trans. Computer-Aided Design, Vol. 13, No. 3, Mar. 1994, pp. 353-358 (hereinafter, the article is referred to as the article A).
As introduced in the second chapter xe2x80x9cPrevious Workxe2x80x9d in the article A, test pattern compaction is grouped into static compaction and dynamic compaction. In the static compaction, all test patterns which can detect faults are generated before test pattern compaction is carried out, and thereafter, test pattern compaction is carried out independently of generation of test patterns. In the dynamic compaction, automatic generation of test patterns which can detect faults and test pattern compaction for reducing the total number of test patterns are simultaneously carried out.
FIG. 1 is a flow chart showing steps to be carried out in the test pattern compaction in accordance with the first prior art. The test pattern compaction disclosed in the first prior art belongs to static compaction, and carries out the steps shown in FIG. 1 to conduct test pattern compaction.
With reference to FIG. 1, first, circuit data and fault data are received, in the step S2001.
Then, there is generated test patterns to detect all faults, in the step S2002.
Then, arrangement of the thus generated test patterns is varied, in the step S2003.
Then, a logical value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is assigned to a primary input (PI) having a uncertain value (X value), among the test patterns, to thereby re-activate the test patterns, in the step S2004.
Then, fault simulation is conducted to the re-activated test patterns to identify the primary inputs which are not relevant to detection of all the faults, in all the test patterns, and assign uncertain values to the primary inputs, in the step S2005.
Then, test patterns which can be combined to one another are combined to one another among the test patterns to which the uncertain values were assigned, to thereby reduce the number of the test patterns, in the step S2006.
If the number of the test patterns is not adequately reduced, the steps S2003 to S2006 are repeated. If the number of the test patterns is adequately reduced, the compacted test patterns are output externally, in the step S2007. Thus, the test pattern compaction is completed.
FIG. 2 is a flow chart showing steps to be carried out in the test pattern compaction disclosed in the second prior art. The test pattern compaction disclosed in the second prior art belongs to dynamic compaction, and carries out steps shown in FIG. 2 to generate test patterns.
Generation of test patterns starts in the step S2101, and then, there is made a fault list indicating faults to which test patterns are to be generated, in the step S2102.
Then, it is checked as to whether all faults are detected, in the step S2103.
If all the faults are detected (YES in the step S2103), generation of test patterns is finished in the step S2114.
If all the faults are not detected (NO in the step S2103), one of the faults is selected from the fault list at that time, in the step S2104. The thus selected fault is called a target fault.
Then, it is checked as to whether the test patterns having been generated so far have detected the target fault, in the step S2106.
If the target fault has been detected (YES in the step S2105), the step S2103 is repeated.
If the target fault has not been detected (NO in the step S2105), a test pattern for detecting the target fault is generated, in the step S2106.
Then, it is checked as to whether the thus generated test pattern is single or not, in the step S2107.
If the generated test patter is plural (NO in the step S2107), it is checked as to whether a plurality of test patterns is selected among the test patterns, in the step S2109.
If a plurality of test patterns is selected (YES in the step S2109), fault simulation is conducted to one of the test patterns, in the step S2110.
Then, the number of faults having been detected in the test pattern to which the fault simulation was conducted is recorded, in the step S2111. The steps S2110 and S2111 are carried out to all the test patterns selected in the step S2109.
If only one test pattern remains (NO in the step S2109), a test pattern which detected faults most is selected as a test pattern for the target fault, in the step S2112.
Then, the fault list is updated in the step S2113. Thereafter, the step S2103 is repeated.
However, the above-mentioned first and second prior art are accompanied with problems, as follows.
The steps S2003 and S2006 in the first prior art can not be applied to a sequential circuit, and hence, it is not possible to repeat those steps for enhancing advantages obtained by those steps. As a result, the first prior art is accompanied with a problem that an advantage of enhancing the test pattern compaction by repeating those steps can not be obtained in a sequential circuit.
The test pattern compaction disclosed in the second prior art is accompanied with a problem that since the fault simulation is conducted to each of the test patterns selected in the step S2110, the number of the fault simulation unavoidably increases, and it would take much time to conduct the fault simulation.
Japanese Unexamined Patent Publication No. 9-145800 has suggested a method of generating a test pattern, including the steps of (a) selecting a fault to be detected, in a circuit for which a test pattern is generated, (b) selecting a target fault among the faults having been identified in the step (a), (c) generating a test pattern for the target fault, (d) conducting fault simulation to the test patterns generated in the step (c) with respect to all the faults selected in the step (a), and (e) determining faults which cannot be detected by means of the test patterns, as target faults. The steps (c) to (e) are repeated to generate test patterns which can detect all the faults selected in the step (a).
Japanese Unexamined Patent Publication No. 7-55895 has suggested a method of generating a test pattern for detecting a fault in LSI, including the steps of detecting a fault by means of each of test patterns separated into individual patterns by reset signals which initializes a sequential circuit mounted in LSI, identifying unnecessary test patterns, based on faults having been detected by the test patterns, and removing the unnecessary test patterns to reduce the number of test patterns.
Japanese Unexamined Patent Publication No. 7-191102 has suggested an apparatus for automatically generating a test pattern constituting a test pattern, used for testing a combinational circuit. The apparatus generates a first pattern with which a fault simulator conducts fault simulation. A pair of the first pattern and a fault which can be detected by the first pattern is input into a compacting unit. The first pattern is removed in the compacting unit to thereby compact the test pattern.
Japanese Unexamined Patent Publication No. 6-52005 has suggested a method of generating a test pattern used for testing a sequential circuit, including the steps of (a) connecting a first series to a second series to generate a pattern series which detects a specific transition fault where the first series accomplishes status transition from an initial condition in the status transition to a wrong status of destination, by means of status transition description, (b) generating an extended pattern series which extends other transition faults with values transmitted to a combinational circuit from a memory in each of patterns associated with each of status being in transition by means of the pattern series, being kept as they are, and (c) outputting the patterns to the combinational circuit in synchronization with clock signals, observing output signals transmitted from the combinational circuit, and inputting the extended patterns into the combinational circuit for observing the output signals with the clock signals being kept fixed.
Japanese Unexamined Patent Publication No. 11-83959 has suggested an apparatus for generating a test pattern, including first means for generating test patterns to detect a fault in circuit data, second means for removing a part of the circuit data influenced by test patterns generated by the first means, and third means for merging a test pattern generated by first means for the circuit data before its part is removed by second means, to a test pattern generated by first means for the circuit data after its part has been removed.
Japanese Patent No. 2953975 (Japanese Unexamined Patent Publication No. 8-212799) has suggested an apparatus for generating a test pattern used for testing a logic circuit, including first means for receiving connection data and fault data of a logic circuit, second means for making and outputting input data about a test pattern used for detecting a fault in the logic circuit, third means for assigning the test pattern input data to an input terminal of the logic circuit, fourth means for storing logical values of logic gates and input/output terminals of the logic circuit, based on the test pattern input data assigned to the input terminal, fifth means for defining fault data about a fault to be detected, sixth means for conducting fault simulation to all the faults identified by the fifth means, seventh means for extracting faults detected by the sixth means and removing the thus detected faults from target faults, eighth means for extracting an initial test pattern from all terminals acting as input terminals, based on the test pattern input data in which a fault was detected, ninth means for assigning a uncertain value to input terminals which are not necessary to have certain values, tenth means for storing the test patterns to which a uncertain value is assigned by the eighth means, eleventh means for checking whether faults to be detected exist in the fault data, transmitting an instruction of generating a test pattern, to the second means, if faults to be detected exist in the fault data, and transmitting an instruction of merging test patterns to one another, if faults to be detected do not exist in the fault data, twelfth means for merging the test patterns read out by the tenth means, to thereby generate a test pattern series, and thirteenth means for outputting the test pattern series merged by the twelfth means.
However, the above-mentioned problems remain unsolved even in the above-mentioned Publications.
In view of the above-mentioned problems in the prior art, it is an object of the present invention to provide a method of and an apparatus for generating a test pattern used for testing a logic circuit, both of which are capable of shortening a length of a test pattern generated by automatic test pattern generation systems used for a sequential circuit and a combinational circuit.
As mentioned later in detail, the present invention solves not only the problem accompanied with the first prior art, but also the problem accompanied with the second prior art to thereby provide a method of and an apparatus for generating a test pattern, both of which have a function of compacting a test pattern.
As mentioned earlier, the first prior art is accompanied with the problem that since the steps S2003 and S2006 can not be applied to a sequential circuit, a process of repeating the steps S2003 to S2006 for enhancing a function of compacting a test pattern can not be applied to a sequential circuit.
In accordance with the present invention, in order to solve the problem, steps corresponding to the steps S2004 and S2005 are repeatedly carried out while a test pattern is being generated, to accomplish dynamic compaction having a function of highly compacting a test pattern.
The method in accordance with the present invention is designed to include the step (corresponding the step S105 explained later in the embodiment) of re-activating a test pattern, in which the step (corresponding to the step S2005) of determining a uncertain value is first carried out, and then, the step (corresponding to the step S2004) of re-activating the uncertain value is carried out. The step of re-activating a test pattern is carried out while the steps corresponding to the steps S2004 and S2005 are being carried out. The step of re-activating a test pattern is introduced into the step of generating a test pattern, and may be carried out a plurality of times. As a result, test pattern compaction can be effectively carried out during the step of generating a test pattern. That is, the present invention accomplishes an enhanced function of dynamic compaction by applying the step of re-activating a test pattern to the step of generating a test pattern. In the step of generating a test pattern, a test pattern is generated to a fault to be detected, and there is generated a test sequence necessary for detecting the fault. Herein, a test sequence is defined as a sum of test patterns comprised of at least one test pattern having a positional relation among one another which relation is necessary for detecting a fault. By re-activating the test sequence a plurality of time in the step of re-activating a test pattern, it is possible to update a test sequence generated for detecting only one fault, into a test sequence capable of detecting one or more faults. The above-mentioned process may be applied to not only a sequential circuit, but also a combinational circuit.
In the above-mentioned second prior art, when a target fault can be detected by a plurality of test patterns, fault simulation is conducted to each of the test patterns, and a test pattern which detected faults most is selected as a test pattern to be used for the target fault. By combining this function with the solution to the above-mentioned problem in the first prior art, it would be possible to further enhance a function of test pattern compaction obtained by the solution to the problem accompanied with the first prior art, That is, the step (later mentioned step S105 in the embodiment) of re-activating a test pattern includes the step of determining a uncertain value, corresponding to the step S2005, and the step of re-activating a uncertain value, corresponding to the step S2004. The method in accordance with the present invention is designed to include, as an extended step of the step of re-activating a uncertain value, the steps of making copies of the test sequence having those uncertain value, and assigning a logical value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d selected through pseudo-random number, to primary inputs having the uncertain value. As a result, there can be generated a plurality of test sequences each comprised of different test patterns. The thus generated test sequences are test sequences which can always detect a fault selected in the step of selecting a fault to be detected (later mentioned step S103 in the embodiment). Fault simulation is conducted to each of the test sequences in accordance with the test pattern compaction process disclosed in the second prior art, to find a test sequence which can detect faults most. Thus, the present invention makes it possible to detect a greater number of faults than the above-mentioned first and second prior art.
As is obvious in the problem accompanied with the second problem, since it takes much time to conduct fault simulation in accordance with the test pattern compaction disclosed in the second prior art, there may be used a parallel pattern parallel fault process in order to shorten a period of time for conducting fault simulation.
The above-mentioned parallel pattern parallel fault (PPPF) process is introduced in the following article, for instance: M. B. Amin and B. Vinakota, xe2x80x9cZAMBEZI: A Parallel Pattern Parallel Fault Sequential Circuit Fault Simulatorxe2x80x9d, 1996 14th IEEE VLSI Test Symposium.
By using the PPPF simulation, it would be possible to concurrently conduct fault simulation to a plurality of faults, ensuring that fault simulation can be conducted at a high rate and the problem accompanied with the second prior art can be solved.
The later mentioned step S105 of re-activating a test pattern is comprised of a combination of the step S2004 extended by the PPPF simulation and the step S2005.
Hereinbelow is explained the PPPF simulation with reference to FIGS. 3A-3C, 4A-4C and 5A-5B. FIGS. 3A to 3C show the PPPF simulation, FIGS. 4A to 4C show the conventional fault simulation or SPPF simulation, and FIGS. 5A and 5B show the PPPF simulation.
Hereinbelow, fault definition illustrated in FIG. 3C is applied to a circuit 3101 illustrated in FIG. 3A, and fault simulation is conducted through the use of a test pattern set illustrated in FIG. 3B.
The circuit 3101 illustrated in FIG. 3A is comprised of a first external input terminal A, a second external input terminal B, an external output terminal D, a buffer device C1, and a 2-input AND gate C2 electrically connected to an output terminal of the buffer device C1.
In the fault definition, one degeneracy fault at the side of the first input terminal A of the 2-input AND gate C2 is defined as Fa1, and zero degeneracy fault at the side of the second input terminal B of the 2-input AND gate C2 is defined as Fb0.
The test pattern set illustrated in FIG. 3B includes a first test pattern T1 which applies a logical value xe2x80x9c0xe2x80x9d to the first external input terminal A and a logical value xe2x80x9c1xe2x80x9d to the second external input terminal B, and a second test pattern T2 which applies a logical value xe2x80x9c1xe2x80x9d to the first external input terminal A and a logical value xe2x80x9c1xe2x80x9d to the second external input terminal B.
In accordance with the conventional fault simulation, illustrated in FIGS. 4A to 4C, in which fault simulation is conducted to a plurality of faults through a plurality of test patterns, the fault simulation has to be conducted twice, that is, first fault simulation through the test pattern T1, illustrated in FIG. 4B, and second fault simulation through the test pattern T2, illustrated in FIG. 4C.
FIG. 4A shows a rule to indicate logical values. In the prior art, a logical value for a test pattern and logical values for the faults Fa1 and Fb0 are represented with two regions each having a 2-bit width. Assuming that one word is comprised of 32 words in a computer, it would be possible to deal with 32 different signals, because a logical value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d of a certain signal can store 32 different logical values per one word. In the conventional fault simulation illustrated in FIGS. 4A to 4C, only two bits out of 32 bits are used for conducting fault simulation.
FIGS. 5A and 5B show the PPPF simulation in which a plurality of faults is simulated at a time through a plurality of test patterns. FIG. 5A shows a rule to indicate logical values. As shown in the rule, the first test pattern T1, the second test pattern T2, and logical values for the faults Fa1 and Fb0 can be represented with a 4-bit region, in the PPPF simulation. Hence, it would be possible to detect the faults Fa1 and Fb0 by conducting the fault simulation once, as illustrated in FIG. 5B showing the fault simulation to be conducted through the first and second test patterns T1 and T2.
As mentioned above, since the PPPF simulation illustrated in FIGS. 5A and 5B can use a capacity of representing logical values associated wit one word, as effectively as possible, the PPPF simulation can be conducted to a plurality of faults through a plurality of test patterns more rapidly than the conventional fault simulation illustrated in FIGS. 4A to 4C.
The conventional fault simulation illustrated in FIGS. 4A to 4C is called single pattern parallel fault (SPPF) simulation.
Specifically, in one aspect of the present invention, there is provided a method of generating a pattern for testing a logic circuit, including the steps of (a) judging whether generation of a test pattern is to be finished, (b) selecting a fault for which the test pattern is to be generated, if generation of the test pattern is judged to be continued in the step (a), (c) attempting generating at least one test pattern necessary for detecting the fault selected in the step (b), and (d) carrying out fault simulation to find a test pattern by which undetected faults are detected most, among copies of the at least one test pattern, and re-activating the thus found test pattern, if the at least one test pattern is generated in the step (c).
For instance, the step (d) may be comprised of the steps of (d1) identifying a fault which can be detected by means of at least one test pattern, among undetected faults, (d2) identifying external input terminals which are not necessary for detecting a fault, among external input terminals each constituting at least one test pattern, (d3) applying uncertain values to the external input terminals having been identified in the step (d2), (d4) making L copies of the at least one test pattern wherein L is an integer equal to or greater than 2, (d5) applying a first or second logical value to uncertain values in each of the copied test patterns such that the copied test patterns are different from one another, (d6) carrying out fault simulation to undetected faults through the use of the at least one test pattern, and (d7) finding a test pattern by which undetected faults are detected most, among L copies of the at least one test pattern, the thus found test pattern being re-activated in the step (d).
The step (d6) may include the step of sampling one undetected fault out of M undetected faults to select the undetected faults, in which case, the fault simulation to be carried out in the step (d6) is preferably parallel pattern parallel fault (PPPF) fault simulation.
The step (d6) may include the step of carrying out single pattern parallel fault (SPPF) fault simulation to all of undetected faults.
It is preferable that the method further includes the steps of (e) judging whether the step (d) have been carried out N times wherein N is an integer equal to or greater than 1, and (t) carrying out fault simulation to undetected faults having not been detected, if the step (d) have been carried out N times.
It is preferable that the method further includes the step of repeating the step (d), if the step (d) have not been carried out N times.
It is preferable that the method further includes the step of outputting the test pattern having been re-activated in the step (d), to an external memory.
For instance, generation of a test pattern is finished or not in the step (a) in accordance whether at least one of a fault detecting rate, the number of test patterns, a period of time necessary for generating a test pattern, and the number of undetected faults meets a desired condition.
For instance, generation of a test pattern is finished, if at least one of following conditions is realized: (A) a fault detecting rate is equal to or greater than a desired fault detecting rate, (B) the number of test patterns is equal to or greater than the desired number of test patterns, (C) a period of time necessary for generating a test pattern is equal to or longer than the desired period of time necessary for doing the same, and (D) the number of undetected faults is equal to zero.
It is preferable that the method further includes the step of receiving circuit data and fault data both necessary for generating a test pattern, from an external memory.
It is preferable that the method further includes the step of transmitting data about all generated test patterns and data about all corrected faults to an external memory, if generation of a test pattern is judged to be finished in the step (a).
It is preferable that the method further includes the step of repeating the step (a), if the at least one test pattern is not generated in the step (c).
It is preferable that the method further includes the step of selecting the first or second logical value through pseudo-random number.
There is further provided a method of generating a pattern for testing a logic circuit, including the steps of (a) judging whether generation of a test pattern is to be finished, (b) receiving at least one test pattern from an external memory, if generation of the test pattern is judged to be continued in the step (a), (c) checking whether a fault is detected in all test patterns having been received in the step (b), if a circuit to be tested is a combinational circuit, and (d) carrying out fault simulation to find a test pattern by which undetected faults are detected most, among copies of the at least one test pattern, and re-activating the thus found test pattern, if the fault is detected in the step (c).
It is preferable that the method further includes the step of abandoning the all test patterns, if the fault is not detected, and repeating the step (a).
There is further provided a method of generating a pattern for testing a logic circuit, including the steps of (a) judging whether generation of a test pattern is to be finished, (b) receiving at least one test pattern from an external memory, if generation of the test pattern is judged to be continued in the step (a), (c) generating at least one test pattern, based on a test pattern which detects a fault, if a circuit to be tested is a sequential circuit, and (d) carrying out fault simulation to find a test pattern by which undetected faults are detected most, among copies of the at least one test pattern, and re-activating the thus found test pattern.
The method may further include the step of storing a test pattern which does not detect a fault, in a memory, and repeating the step (a) when a test pattern which detects a fault is input into the memory.
It is preferable that the at least one test pattern in generated in the step (c), based on the test pattern which detects a fault, in combination with the test pattern stored in the memory.
In another aspect of the present invention, there is provided an apparatus for generating a pattern for testing a logic circuit, including (a) a judge which judges whether generation of a test pattern is to be finished, (b) a selector which selects a fault for which the test pattern is to be generated, if generation of the test pattern is judged to be continued in the step (a), (c) a pattern generator which attempts generating at least one test pattern necessary for detecting the fault selected by the selector, and (d) a simulator which carries out fault simulation to find a test pattern by which undetected faults are detected most, among copies of the at least one test pattern, and re-activates the thus found test pattern, if the at least one test pattern is generated by the pattern generator.
For instance, the fault simulator may be comprised of (d1) a first identifier which identifies a fault which can be detected by means of at least one test pattern, among undetected faults, (d2) a second identifier which identifies external input terminals which are not necessary for detecting a fault, among external input terminals each constituting at least one test pattern, (d3) a first device which applies uncertain values to the external input terminals having been identified by the second identifier, (d4) a copier which makes L copies of the at least one test pattern wherein L is an integer equal to or greater than 2, (d5) a second device which applies a first or second logical value to uncertain values in each of the copied test patterns such that the copied test patterns are different from one another, (d6) a fault simulator which carries out fault simulation to undetected faults through the use of the at least one test pattern, and (d7) a detector which finds a test pattern by which undetected faults are detected most, among L copies of the at least one test pattern, the thus found test pattern being re-activated by the simulator.
It is preferable that the fault simulator includes a sampler for sampling one undetected fault out of M undetected faults to select the undetected faults.
It is preferable that fault simulator carries out parallel pattern parallel fault (PPPF) fault simulation to the undetected faults.
It is preferable that the fault simulator carries out single pattern parallel fault (SPPF) fault simulation to all of undetected faults.
The apparatus may further include (e) a judge which judges whether the simulator have carried out re-activation of the test pattern N times wherein N is an integer equal to or greater than 1, and (f) a simulator which carries out fault simulation to undetected faults having not been detected, if the simulator have carried out the re-activation N times.
The apparatus may further include a device which outputs the test pattern having been re-activated, to an external memory.
It is preferable that the judge judges whether generation of a test pattern is to be finished in accordance whether at least one of a fault detecting rate, the number of test patterns, a period of time necessary for generating a test pattern, and the number of undetected faults meets a desired condition.
For instance, generation of a test pattern is finished, if at least one of following conditions is realized: (A) a fault detecting rate is equal to or greater than a desired fault detecting rate, (B) the number of test patterns is equal to or greater than the desired number of test patterns, (C) a period of time necessary for generating a test pattern is equal to or longer than the desired period of time necessary for doing the same, and (D) the number of undetected faults is equal to zero.
The apparatus may further include a receiver which receives circuit data and fault data both necessary for generating a test pattern, from an external memory.
The apparatus may further include a device which transmits data about all generated test patterns and data about all corrected faults to an external memory, if generation of a test pattern is judged to be finished.
It is preferable that the second device selects the first or second logical value through pseudo-random number.
There is further provided an apparatus for generating a pattern for testing a logic circuit, including (a) a judge which judges whether generation of a test pattern is to be finished, (b) a receiver which receives at least one test pattern from an external memory, if generation of the test pattern is judged to be continued by the judge, (c) a checker which checks whether a fault is detected in all test patterns having been received by the receiver, if a circuit to be tested is a combinational circuit, and (d) a simulator which carries out fault simulation to find a test pattern by which undetected faults are detected most, among copies of the at least one test pattern, and re-activates the thus found test pattern, if the fault is detected by the checker.
There is still further provided an apparatus for generating a pattern for testing a logic circuit, including (a) a judge which judges whether generation of a test pattern is to be finished, (b) a receiver which receives at least one test pattern from an external memory, if generation of the test pattern is judged to be continued by the judge, (c) a pattern generator which generates at least one test pattern, based on a test pattern which detects a fault, if a circuit to be tested is a sequential circuit, and (d) a simulator which carries out fault simulation to find a test pattern by which undetected faults are detected most, among copies of the at least one test pattern, and re-activates the thus found test pattern.
The apparatus may further include a memory which stores a test pattern which does not detect a fault, and wherein the judge judges whether generation of a test pattern is to be finished, when a test pattern which detects a fault is input into the memory.
It is preferable that the pattern generator generates the at least one test pattern, based on the test pattern which detects a fault, in combination with the test pattern stored in the memory.
The advantages obtained by the aforementioned present invention will be described hereinbelow.
As explained in the later mentioned first embodiment, the first advantage is that a function of compacting test patterns, obtained by repeating the step of re-activating a test pattern, during the step of generating a test pattern, and a function of compacting test patterns, obtained by identifying a test pattern which detects undetected fault most among a plurality of test patterns used in the repeating step, can be compatible at a high rate by using the PPPF simulation. As a result, it would be possible to enhance both of the functions, and provide the dynamic compaction process having an enhanced function of test pattern compaction.
As explained in the later mentioned second embodiment, the second advantage is that the present invention can be applied not only to dynamic compaction, but also static compaction, if slight modification were made.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.